Verilator simulation time setting problem

When using Verilator, I encountered the problem of insufficient simulation time. For example, when using spi communication, there are only two cycles to view the clock sck_o in gtkwave. How should I change the simulation time when I want to see the simulation results (I have tried to change the end second from the start second to the end second, but it has no effect. I think the simulation time should be set regardless of gtkwave, but related to the verilator setting)

How does this relate the PlatformIO tool? You seem to have a problem with the Verilator tool or gtkwave displaying something wrong?

yes, i already solve it