SVD parser rejects valid 64-bit registers — request clarification on which SVD parser PlatformIO uses

PlatformIO IDE
1

I am using a CMSIS-SVD file that defines some registers with <size>64</size> (64-bit registers).
When loading this SVD in PlatformIO (via debug_svd_path), the following error occurs:

Register AES_INPUT has invalid size: 64. Should be 8, 16 or 32

However, according to the CMSIS-SVD specification, the <size> element is a non-negative integer specifying the number of bits of the register.
There is no restriction limiting it to 8, 16, or 32 bits.

This makes 64-bit registers perfectly valid SVD constructs.
It seems that PlatformIO’s SVD parser enforces an arbitrary constraint that conflicts with the official specification.

Could you please clarify which SVD parser PlatformIO uses internally, and where in the codebase it resides (e.g. in platformio-core, the VSCode extension, or an external library)?

I’d like to review the implementation to understand this limitation and potentially contribute a fix or patch to support 64-bit registers.