Hi,
I’m very sorry for this very belated reply! I did saw it right after you made the post but kinda had to go to bed and forgot to respond each weekend after it till now
Again, sorry for that!
So i followed your suggestion and initially got this output:
❯ ./bin/openocd -s share/openocd/scripts -f interface/ftdi/sipeed-rv-debugger.cfg -c "set ESP32_FLASH_VOLTAGE 3.3" -f target/esp32.cfg
Open On-Chip Debugger v0.10.0-esp32-20201202 (2020-12-02-17:38)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
3.3
Warn : Transport "jtag" was already selected
Info : FreeRTOS creation
Info : FreeRTOS creation
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Error: An adapter speed is not selected in the init script. Insert a call to adapter_khz or jtag_rclk to proceed.
openocd: ../src/jtag/core.c:343: jtag_checks: Assertion `jtag_trst == 0' failed.
[1] 198256 abort (core dumped) ./bin/openocd -s share/openocd/scripts -f -c "set ESP32_FLASH_VOLTAGE 3.3" -
After googling a bit it looked like i had to set adapter_khz
and i did that to the clock speed of this chip.
So my sipeed-rv-debugger.cfg
now looks like:
interface ftdi
ftdi_device_desc "Dual RS232"
ftdi_vid_pid 0x0403 0x6010
adapter_khz 6000
#autoexit true
#interface cmsis-dap
transport select jtag
ftdi_layout_init 0x0008 0x001b
ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
It does seem fix it as the output now is:
❯ ./bin/openocd -s share/openocd/scripts -f interface/ftdi/sipeed-rv-debugger.cfg -c "set ESP32_FLASH_VOLTAGE 3.3" -f target/esp32.cfg
Open On-Chip Debugger v0.10.0-esp32-20201202 (2020-12-02-17:38)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
3.3
Warn : Transport "jtag" was already selected
Info : FreeRTOS creation
Info : FreeRTOS creation
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : clock speed 6000 kHz
Info : JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : esp32.cpu0: Detected debug stubs @ 3ffc1fe8
Info : esp32.cpu1: Debug controller was reset.
Info : esp32.cpu1: Core was reset.
Info : esp32.cpu1: Detected debug stubs @ 3ffc1fe8
Info : Listening on port 3333 for gdb connections
Which leads me to think that everything is now setup properly.
However, getting it running in platformio still seems to be a bit of a challenge.
I think - very uncertain… - that i need to set a debug server with this in platformio.ini:
debug_tool = custom
debug_port = localhost:3333
debug_init_break = tbreak setup
Mind you, this does work and after a few minutes it does end up in the setup function!
So yes, we’re getting there!
But each debug step is taking so freaking long! As in about 5 seconds for each step i do! Is that how it’s supposed to work?
Also, using the sipeed-rv-debugger
still gives the very same error as the initial post i made. Isn’t that supposed to be working now with that adapter config that i added?
Thank you so much for your help thus far!