Hi,
I’m trying to create a new custom platform from scratch for compiling code for a custom RISC-V core that I implemented on FPGA.
So I need to pack a toolchain and the implementation of my system calls for NewLib. I started a to build a platform but nothing works, and now I’m not sure what I’m doing or that I’m doing what it’s really needed.
In my case I created also the framework to include an LD script, the sys calls and a startup code, but I don’t know if it is necessary.
I also need to understand how to install the platform and the tools created.
Here the platform can be founded.
(sorry for the italian readme but I have no intention to public this platform)
If someone can help me to fix it I will be grateful.
The toolchain and framework packages usually do not reside within the platform. They are however referenced by the platform’s platform.json with the version expression detailing how to obtain that package; for examle
Hi Max,
excuse me for the delay but email notification were turned off…
So, replying to you:
I made some changes (in the repo linked before):
I modified the branch ‘compilazione’ to use the “version” key moving in separate repos the toolchain and the framework (both published on my GH) and now the installation its OK.
Create a new branch based on ‘compilazione’ to use the official RISC-V toolchain (that for now it’s sufficient)
In both brances I got some errors (at the end of the reply I’ll link a project to test):
cc1 is not found using my custom toolchain. I think this may be because I just copied the compiled toolchain directory to the repo. I’m not an expert, so I’m not sure if this will work, but I think recompiling the toolchain with the right configuration might solve the problem. However, I would like some suggestions before doing this.
Using the original toolchain i got:
*** Do not know how to make File target `checkprogsize' (/home/alan.masutti/Documents/PlatformIO/Projects/testPlatform/checkprogsize). Stop.
This is the project for testing the platform. I only need ad ELF file, after I got it, I got a python script that’s generate an header file with raw sections and addresses of the executable, this will be included in a firmware that, through ARM Processing System, load it to my SoftCore on the FPGA but this is a further step.
I hope that you find this information helpful to got the point.