HSE Clock Setup

Development Platforms
11

The code you provided runs fine on my bluepill for 9600 baud and produces

Hello 5833 56000000

however your ms_delay(1000); doesn’t give 1000 ms delay because it’s a NOP loop with a constant 500 NOPs per millisecond so that won’t work on all frequences. Systick timer is better here.

Anyways I corrected your PLL code by just doing equal things as this does. You set the wrong PLL multiplier and also forget to modify the flash wait states, so code can’t be able tun run after this.

Corrected method:

void setSystemFreq()
{
	RCC->CIR = 0x009F0000;

    // Turn HSE ON
    RCC->CR |= RCC_CR_HSEON;

    // Wait Until HSE Is Ready
    while (!(RCC->CR & RCC_CR_HSERDY))
        ;
    serialPrint("HSE ON\n");

    //set HSE as system clock
    RCC->CFGR = (RCC->CFGR & ~(RCC_CFGR_SW)) | RCC_CFGR_SW_HSE;

    //AHB prescaler
    RCC->CFGR &= ~(RCC_CFGR_HPRE); //remove old prescaler
    RCC->CFGR |= RCC_CFGR_HPRE_DIV1; //set AHB prescaler = 1.
    //set ADC prescaler = 8
    RCC->CFGR &= ~(RCC_CFGR_ADCPRE);
    RCC->CFGR |= RCC_CFGR_ADCPRE_DIV8;
    //set APB1 prescaler
    RCC->CFGR &= ~(RCC_CFGR_PPRE1);
    RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
    //set APB2 prescaler
    RCC->CFGR &= ~(RCC_CFGR_PPRE2);
    RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;

    //set flash wait states to 2 wait states
    FLASH->ACR &= ~(FLASH_ACR_LATENCY);
    FLASH->ACR |= FLASH_ACR_LATENCY_2;

    //Set PLL Multiplier
    //RCC->CFGR |= 0b1100 << 18;
    //at HSE=8MHz, 8*9 = 72MHz.
    RCC->CFGR &= ~(RCC_CFGR_PLLMULL);
    RCC->CFGR |= RCC_CFGR_PLLMULL9;

    // //Set HSE as PLL Source. bit set -> HSE, bit unser -> HSI
    RCC->CFGR |= RCC_CFGR_PLLSRC;

    // Set HSE Prescaler On PLL Entry
    RCC->CFGR &= ~RCC_CFGR_PLLXTPRE;
    RCC->CFGR |= RCC_CFGR_PLLXTPRE_HSE; //no HSE prescaler before PLL entry


    // Turn On PLL Clock
    RCC->CR |= RCC_CR_PLLON;
    serialPrint("wait for PLL ON\n");
    //ms_delay(1000);

    // Wait Until PLL Is Ready
    while (!(RCC->CR & RCC_CR_PLLRDY))
        ;
    serialPrint("PLL rdy\n");

    //serialPrint("Clock ON\n");
    //ms_delay(1000);
    // Set System To PLL CLock
    RCC->CFGR = (RCC->CFGR & ~(RCC_CFGR_SW)) | RCC_CFGR_SW_PLL;
    serialPrint("switched to PLL clock\n");


    // Clear All Interrupts
    RCC->CIR = 0x009F0000;
}

outputs (with extra prints in clock source enabled)

Hello 7500 72000000
Clock Source : 1
AHB_Prec : 0
Pll_Multiplier : 9
PLL_Source : 1
HSE_Prec : 0
PLL_Freq : 72000000
SystemCoreClock : 72000000

So you have your 72MHz now and the UART still works at 9600 baud.